1. Mips Instruction Set Branch Delay Slot
2. Mips Branch Delay Slot Instructions

When the processor executes an instruction, the program counter is advanced during the Instruction Fetch (IF) stage. Due to the pipeline structure where when a jump or branch is being executed and the instruction afterwards would also be put into the pipeline, MIPS implements something called the branch delay slot. Branch delay instruction Branch Instruction + 2 BEQZ R1, L1 branch delay instruction instruction + 2 instruction + 3 L1: branch target branch target + 1 branch target + 2. Instruction immediately following branch is executed irrespective of whether the branch is taken or not. Rely on compiler to make successor instructions valid. A branch delay slot follows the instruction. Bgt s,t,addr pseudo branch if s t A branch delay slot follows the instruction. Ble s,t,addr pseudo branch if s branch delay slot follows the instruction. Blez s,addr normal branch if the two's comp. Integer in register s is branch delay slot follows the instruction. The real MIPS architecture is 'pipelined' to improve efficiency one instruction can start before the previous one finishes For branching instructions (e.g. Instruction following branch is executed before branch completes To avoid potential problems use nop immediately after branch A problem scenario, and its solution (branch delay slot).

Mips Instruction Set Branch Delay Slot

Mips Branch Delay Slot Instructions